By-pass boundary scan design

Details By-pass boundary scan design By-pass boundary scan design

1989-10-27

1991-08-20

Beausoliel, Robert W.

Excavating

371 224, 371 251, G06F 1100, G01R 3128

Patent

active

050420348

ABSTRACT:
The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both. In this configuration data from the storage register can be input into the boundary logic without going through a multiplexer in the data path and incurring the associated delay. The boundary logic can then be self tested using ordinary LSSD techniques. This self testing can also be performed with a minimum of additional silicon area being used for the self test structures.

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F. Beenker, "Systematic and Structured Methods for Digital Board Testing," IEEE International Conference, 1/1985, pp. 380-385.
L. Whetsel, "A Standard Test Bus and Boundary Scan Architecture", Tl Tech. Journal, 7/1988, pp. 48-59.
C. Gloster, "Boundary Scan with Built-In Self-Test" IEEE Design & Test, 2/1989, pp. 36-44.

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