Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-03-27
2001-10-30
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S754000, C257S755000
Reexamination Certificate
active
06310397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to contact resistance of butted contacts in semiconductor memory devices and more particularly to butted contacts in SRAM devices.
2. Description of Related Art
It is difficult to reduce butted contact resistance in sub-half micron SRAM devices because of Si/Si or Si/WSix interfaces. A high resistance node sometimes acts to contribute to killing the yield of a manufacturing process.
U.S. Pat. No. 5,607,881 of Huang for “Method of Reducing Buried Contact Resistance in SRAM” shows an extra ion implant into a trench but not into the polysilicon. A buried contact is formed within a semiconductor substrate by dopant diffusion from an overlying polysilicon layer. The second polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein a portion of the buried contact within said semiconductor substrate is exposed. The polysilicon layer is overetched whereby a trench is etched into the exposed semiconductor substrate. An extra implant is implanted into the semiconductor substrate around the trench.
U.S. Pat. No. 5,393,687 of Liang for “Method of Making Buried Contact Module with Multiple Poly Si Layers” teaches a method of making buried contact module with multiple polysilicon layers.
U.S. Pat. No. 5,596,215 of Huang for “Method to Improve Buried Contact Resistance” teaches a method for filling a conductive trench in a buried contact.
U.S. Pat. No. 5,668,051 of Chen et al for “Method of Forming Poly Plug to Reduce Buried Contact Resistance” describes driving dopant from a second polysilicon layer to form a buried contact junction and etching away the second polysilicon layer where a planned source/drain region will be formed adjacent to the buried contact junction.
An object of this invention is to reduce butted contact resistance because of lower resistivity in the contact area.
SUMMARY OF THE INVENTION
A two stage, lower energy/higher energy phosphorous implantation is performed at the Vcc implantation stage. The first implantation is performed at an energy of 35 keV, followed by an second more penetrating implant at an energy of 50 keV. This extra implantation depth should be aimed at the contact interface to add extra P type impurity within this area. Butted contact resistance is reduced because of lower resistivity in the contact area. The reduction of contact resistance enhances the immunity of SRAM devices, if low resistance is required for the butted contacts.
A device in accordance with this invention is provided by a method, also in accordance with this invention, of forming a butted contact in an SRAM memory device comprises providing the SRAM memory device with a butted contact exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer on the surface of the device with an opening framing the contact region and the butt end of the conductor stack adjacent to the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the interpolysilicon silicon oxide dielectric layer, the contact region, and the butt end of the conductor stack. Pattern the undoped upper polysilicon into interconnect and load resistance parts. Form a Vcc mask with an open window framing framing the interconnect part of the undoped upper polysilicon layer, the contact region, and the butt end of the conductor stack. Ion implant a first dose of Vcc dopant through the window into the upper polysilicon layer at a first energy level, and then ion implant a second dose of Vcc dopant through the window into the buried contact region and the butt end of the conductor stack layer at a higher energy level than the first energy level.
Preferably, the upper polysilicon layer is implanted with the first dose comprising phosphorus of from about 2 E 15 ions/cm
2
to about 6 E 15 ions/cm
2
at an energy from about 30 keV to about 40 keV, preferably about 4 E 15 ions/cm
2
Vcc dopant at an energy of 35 keV. After annealing the phosphorus dopant in the upper polysilicon layer has a concentration of is from about 2 E 20 atoms/cm
3
to about 6 E 20 atoms/cm
3
, and the buried contact region and the butt end of the conductor stack are implanted with the second dose of about 4 E 15 ions/cm
2
Vcc of phosphorus dopant an energy from about 45 keV to about 55 keV, preferably at an energy of 50 keV, and after annealing the concentration of phosphorus dopant in the upper polysilicon layer is from about 2 E 20 atoms/cm
3
to about 6 E 20 atoms/cm
3
.
After implanting the second dose of Vcc dopant the photoresist layer PR is been stripped from the device.
The next step is to perform load implantation.
REFERENCES:
patent: 5393687 (1995-02-01), Liang
patent: 5596215 (1997-01-01), Huang
patent: 5607881 (1997-03-01), Huang
patent: 5668051 (1997-09-01), Chen et al.
patent: 5686334 (1997-11-01), Sundaresan
patent: 5751044 (1998-05-01), Lee
patent: 6107642 (2000-08-01), Sundaresan
patent: 6239458 (2001-05-01), Liaw et al.
Chang Yeong-Kong
Liao Hung-Che
Ackerman Stephen B.
Jones II Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Wilson Allan R.
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