Busy signal interface between master and slave processors in a c

Details Busy signal interface between master and slave processors in a c Busy signal interface between master and slave processors in a c

1984-08-27

1987-03-03

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1516

Patent

active

046480340

ABSTRACT:
A 32-bit central processing unit (CPU) having a six-stage pipeline architecture with an instruction and data cache memory and a memory management units, all provided on a single, integrated circuit (I.C.) chip. The CPU also contains means for controlling the operation of a separate I.C. chip co-processor that is dedicated to performing specific functions at a very high rate of speed, commonly called an extended processing unit (EPU). The EPU is provided with interface circuits that generate control signals and communicate them to the controlling CPU.

REFERENCES:
patent: 3940743 (1976-02-01), Fitzgerald
patent: 3962685 (1976-06-01), Belle Isle
patent: 4224664 (1980-09-01), Trinchieri
patent: 4270167 (1981-05-01), Koehler et al.
patent: 4547849 (1985-10-01), Louie et al.

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