Bus window interlock

Details Bus window interlock Bus window interlock

1987-09-04

1990-01-30

Kemeny, Emanuel S.

Boots, shoes, and leggings

G06F 1516, G06F 946

Patent

active

048977861

ABSTRACT:
A system for implementing a bus window interlock scheme between a first and a second bus utilizes two bus window modules. The first bus window module coupled to the processor bus includes an interlock state bit which is set upon the acceptance of an interlock transaction from a processor. No further interlock transactions will be accepted while the interlock state bit is set. The interlock transaction is passed to a transaction buffer in the second bus window module which is coupled to memory through the memory bus. The transaction buffer passes the interlock data for memory to the memory bus while simultaneously loading a one deep interlock buffer. A confirmation is sent from the memory back to the transaction buffer. If the confirmation is interlock busy, then the interlock transaction is retried from the interlock buffer thus allowing the transaction buffer to process other commands. The interlock buffer waits for an unlock write signal before retrying an interlock transaction thus alleviating congestion on the memory bus.

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patent: 4547845 (1985-10-01), Ross
patent: 4570217 (1986-02-01), Arlen et al.
patent: 4713834 (1987-12-01), Brahm et al.

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