Bus to bus bridge deadlock prevention system

Details Bus to bus bridge deadlock prevention system Bus to bus bridge deadlock prevention system

1997-03-25

1999-03-30

Scheikh, Ayaz R.

Pulse or digital communications

Repeaters

Testing

375287, G06F 1340, G06F 1314

Patent

active

058899723

ABSTRACT:
A bus to bus bridge deadlock prevention system detects and resolves a deadlock condition in a bus to bus bridge. In a PCI protocol application of the present invention, the system detects a retry of a request by a master device. The request is masked for a delay period before the request is allowed to attempt to pass through a PCI to PCI bridge. If the request results in a further retry, the delay period length is changed and the request is masked for the different delay period. Successive retry requests are masked for different delay periods until the deadlock condition is resolved. The system adapts to the deadlock condition by repeatedly changing the delay period until the deadlock condition is resolved and the bridged busses resume normal operation.

REFERENCES:
patent: 5542056 (1996-07-01), Jaffa et al.
patent: 5625779 (1997-04-01), Soloman et al.
patent: 5632021 (1997-05-01), Jennings et al.
Digital Semiconductor 21052 PCI-to-PCI Bridge Data Sheet, Digital Equipment Corporation, pp. iii-A-2, Jan. 1996.
PCI Local Bus Specification Rev. 2.1; Jun. 1, 1995, pp. 32, 41, 43, 44, 115, and 116.

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