Bus termination resistance linearity circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307361, 307491, 307568, H03H 11100

Patent

active

053592352

ABSTRACT:
An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. The termination further includes a circuit to linearize the impedance as a function of the reference voltage. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

REFERENCES:
patent: 3810035 (1974-05-01), Gundry
patent: 4236126 (1980-11-01), Weller et al.
patent: 4378536 (1983-03-01), Schwarzmann
patent: 4520282 (1985-05-01), Watanabe et al.
patent: 4689576 (1987-08-01), Wisseman
patent: 4920339 (1990-04-01), Friend et al.
patent: 5029284 (1991-07-01), Felbaumer et al.

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