Boots – shoes – and leggings
Patent
1992-12-24
1996-06-18
Lee, Thomas C.
Boots, shoes, and leggings
395287, 3642426, 3642401, 36424341, 36424292, G06F 13364
Patent
active
055287646
ABSTRACT:
A Peripheral Component Interconnect (PCI) bus for component level interconnection of processors, peripherals and memories. The PCI bus is a physical interconnect apparatus intended for use between highly integrated peripheral controller components and processor/memory systems. The PCI bus is intended as a standard interface at the component level in much the same way that ISA, EISA, or Micro Channel.TM. buses are standard interfaces at the board level. Just as ISA, EISA, and Micro Channel.TM. buses provide a common I/O board interface across different platforms and different processor generations, the PCI bus is intended to be a common I/O component interface across different platforms and different processor generations. The PCI bus lends itself to use as a main memory bus, and can be used with various cache memory techniques.
REFERENCES:
patent: 4161024 (1979-06-01), Joyce et al.
patent: 4933835 (1990-06-01), Sachs et al.
patent: 5067078 (1991-11-01), Talgam et al.
patent: 5072369 (1991-12-01), Theus et al.
patent: 5109493 (1992-04-01), Banerjee
patent: 5249284 (1993-09-01), Kass et al.
patent: 5276887 (1994-01-01), Haynie
patent: 5335335 (1994-08-01), Jackson et al.
patent: 5392407 (1995-02-01), Heil et al.
Gates George
Lee Thomas C.
NCR Corporation
Weinstein Marc K.
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