Bus system for information processing system and method of contr

Details Bus system for information processing system and method of contr Bus system for information processing system and method of contr

1990-04-20

1994-01-04

Fleming, Michael R.

Boots, shoes, and leggings

364DIG1, 364228, 364229, 364230, 3642301, 3642302, 3642304, 3642315, 364240, 3642405, 3642412, 3642413, 3642426, 3642427, 3642429, 36424292, 364260, 3642601, 3642705, 3642706, 3642716, 3642717, G06F 1300

Patent

active

052768180

ABSTRACT:
A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.

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IEEE Standard Backplane Bus Specification for Multiprocessor Architecture: Futurebus, ANSI/IEEE Std. 896.1-1987, pp. 73-119.
IEEE Standard for a Simple 32 bit Backplane Bus Nubus. ANSI/IEEE Std. 1196-1987, 21-62.

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