Bus system for coordinating internal and external direct memory

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3642285, 3642423, 36424231, 36424233, 36424341, 36424531, 364259, 3642592, 364260, 3642603, 3642563, 364240, 36493143, 36492797, 3649412, 36494833, 3649612, 395325, 395400, 395800, G06F 13368, G06F 1328

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053476433

ABSTRACT:
A one-chip microprocessor including an instruction execution unit, a DMA controller, and a memory management unit. The instruction execution unit has a logical address for storing an address to be accessed. The DMA controller has a DMA register for storing an address given when direct memory access is performed. The memory execution unit further includes an address converting means for converting a logical address stored in the logical address register of the instruction execution unit into a physical address to be accessed, a hit determining means for determining whether or not the cache memory connected as an external unit is hit on the basis of the physical address, and a burst transfer circuit for performing burst transfer of the cache memory. The one-chip microprocessor is connected by a bus to a system having a cache memory, a memory controller and a main memory.

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