Bus synchronizing method and system based thereon

Details Bus synchronizing method and system based thereon Bus synchronizing method and system based thereon

1995-03-17

1996-12-24

Olms, Douglas W.

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

H04J 306

Patent

active

055880045

ABSTRACT:
Bus clock generation circuits divide an output of an oscillation circuit with respect to frequency and output phase state signals. A synchronization circuit judges a setup condition on a second bus on the basis of the phase state signals and, when judging the satisfied setup condition, outputs a shift request signal to a CLK2 generation circuit. This causes the CLK2 generation circuit to change a phase of a clock CLK2 in such a manner that data transmission ends always within one period of the clock CLK2, thus a reducing synchronization overhead.

REFERENCES:
patent: 5099477 (1992-03-01), Taniguchi et al.
patent: 5256912 (1993-10-01), Rios
patent: 5276858 (1994-01-01), Oak et al.
patent: 5305452 (1994-04-01), Khan et al.
patent: 5414820 (1995-05-01), McFarland et al.
patent: 5432826 (1995-07-01), Rieder

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