Bus synchronization apparatus and method

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395275, G06F 1300, G06F 112

Patent

active

053718801

ABSTRACT:
Several techniques are used to optimize the transmission of signals or events from one bus to the other. In one aspect, the user of a chipset is permitted to choose whether the originating events (i.e. the events in response to which a destination event is to be generated on a destination bus) are to be generated synchronously or asynchronously with the clock signal on the destination bus. Whether synchronous or asynchronous generation is chosen, the chipset may perform a synchronization function in response to an originating bus predictor signal. The number of destination clock cycles to delay before generating the desired destination bus event is responsive to the relative frequencies of the clock signals on the two buses, thereby accommodating a wide variety of such relative frequencies. In another aspect, for events to be generated on a destination bus synchronously with a clock signal which is by specification stretchable, the destination bus event is generated promptly in response to the originating event and then the destination bus clock signal is stretched to make the destination bus event synchronous with the destination bus clock signal. The length of the stretch is responsive to the relative frequencies of the originating bus and destination bus clock frequencies. A synchronizer is used to generate the destination bus event synchronously with the destination bus clock signal. The user of the chipset can select which formula is to be applied.

REFERENCES:
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5199106 (1993-03-01), Bourke et al.
patent: 5276814 (1994-01-01), Bourke et al.
Intel Corp, 82350 DT Eisa Chipp Set Sep. 1991.
Intel Corp, 82350 Eisa Chip Set Peripheral Components Data Book Jul. 1990.
Texas Instruments Corp, TACT 84500 Eisa Chip Set-Preview Bulletin 1991.
Opti Inc., Opti-386 WB PC/AT Chipset Data Book Mar. 28, 1991.
Opti. Inc, HID 386 AT Chip set High Integration Direct Mapped Cache AT Nov. 1989.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Bus synchronization apparatus and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus synchronization apparatus and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus synchronization apparatus and method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-222191

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.