Bus structure, memory chip and integrated circuit

Details Bus structure, memory chip and integrated circuit Bus structure, memory chip and integrated circuit

2007-01-31

2009-06-30

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S198000, C365S191000

Reexamination Certificate

active

07554875

ABSTRACT:
A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.

REFERENCES:
patent: 6122217 (2000-09-01), Keeth et al.
patent: 6445626 (2002-09-01), Hsu et al.

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