Bus structure for multiprocessor system having separated process

Details Bus structure for multiprocessor system having separated process Bus structure for multiprocessor system having separated process

1994-11-28

1996-12-03

Ellis, Richard L.

395311, G06F 1576, G06F 1340

Patent

active

055817670

ABSTRACT:
The processor section comprises a matrix-line layout of processor units; each processor unit combined with adjacent processor units in row and column direction by means of IPC buses, which are two-way buses. The control/memory section comprises arrays of control/memory units corresponding one-to-one to the processor units; each control/memory unit entering instructions and data simultaneously to the corresponding units in the processor section via optical channels to carry out arithmetic operations. By providing grid-like buses on the control/memory-unit arrays, and transferring instructions and data on the buses and sending them to the processor unit corresponding one-to-one to the control/memory unit to which data are transferred via optical channels, the transfer of instructions and data is carried out efficiently between processor units beyond the third closest ones.

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