Bus structure for an image processor

Details Bus structure for an image processor Bus structure for an image processor

1984-11-21

1986-08-05

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 89, 370 94, H04J 302, H04J 316, H04J 324

Patent

active

046047433

ABSTRACT:
A bus structure for an image processing system connecting a plurality of devices capable of transmitting and receiving packets of N data words serially on N sub-buses wherein the data sub-buses are spatially multiplexed and an address bus is time multiplexed.

REFERENCES:
patent: 4354263 (1982-10-01), Bordry et al.
patent: 4535448 (1985-08-01), Baxter et al.

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