Bus signature analyzer and behavioral functional test method

Details Bus signature analyzer and behavioral functional test method Bus signature analyzer and behavioral functional test method

2000-03-31

2002-07-23

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C714S030000

Reexamination Certificate

active

06424926

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a bus signature analyzer device and method to enable high-speed functional testing of integrated chip components by using a bus enable signal to control signature compression of the bus activities during functional testing.
BACKGROUND
Testing of high speed buses, as well as all of the internal speed paths from a processor to the bus interface, requires high speed and high pin count testers. As technology advances have continued to occur new and faster chips have been developed, which exceed the testing capabilities of existing automatic test equipments (ATEs). Additionally, the ATE solutions that would be required to test these new chips are becoming too costly to build. As a result, speed paths between multiple clock domains are not currently being tested due to the limitations of the available ATEs and structural test techniques.
Initially, equipments and integrated circuits were only functionally tested to determine simply if they worked. This was, and still is, accomplished by coupling an ATE to the piece of equipment or integrated circuit being tested. An example of how an ATE is coupled to a processor chip to test the processor chip is provided in FIG.
1
. In
FIG. 1
, a processor chip
100
is shown to include a central processor unit (CPU)
110
coupled to a cache
120
and a memory controller
130
via a front side bus (FSB)
115
. The memory controller
130
is coupled to an ATE
160
. The ATE
160
is used to test the functionality of the processor chip
100
and the memory controller
130
by receiving bus cycle activity created by the processor chip
100
and the memory controller
130
and comparing this received bus cycle activity with a known defect-free or expected bus cycle activity. If the received and known bus cycle activities match, then the processor chip
100
and the memory controller
130
pass the test and are accepted as good and if the bus cycle activities do not match, then the processor chip
100
and the memory controller
130
fail the test and are rejected. In this configuration, the ATE
160
is used to load the test program through the memory controller
130
and receive the outputs via a bus
162
which couples the ATE
160
to the memory controller
130
. Unfortunately, ATEs have historically only been able to operate at a fraction of the clock speeds of the latest CPUs and memories. For example, while current ATEs can only operate at speed of up to 200 MHz, current generation CPUs and memories can operate at speeds of from 300 to 800 MHz and above and, as a result, the ATE
160
illustrated in
FIG. 1
cannot measure the internal performance of the CPU
110
or the memory controller
130
.
Unfortunately, while this method of ATE testing works well with simple systems and individual integrated circuits, current ATEs are unable to determine the performance of internal speed paths in highly integrated circuits. For example, due to the above noted inherent speed limitations, current ATEs cannot measure the performance of the new generation, fast and highly integrated circuits. Similarly, since the ATE
160
is measuring a combined output result from the memory controller
130
, the ATE
160
is not able to determine what each of the involved components contributed to the result.
Subsequently, structural testing methods and systems were developed called built-in self-test (BIST) to test the individual internal integrated circuits of the equipments. Examples of these methods include a Linear Feedback Shift Register (LFSR) and a Multiple Input Signature Registers (MISR), which is a variant of the LFSR. Both the LFSR and MISR are used to perform signature analysis of the chip being tested. An example of one of many possible configurations of a generic MISR
200
, which can be used as a signature analyzer, is shown in FIG.
2
. In
FIG. 2
, the generic MISR
200
is illustrated in which n-bit D-type flip-flops
210
-
1
-
210
-
n
are serially coupled together and coupled to a feedback circuit
220
to produce compressed signatures on every clock cycle. While the feedback circuit is shown feeding back an output signal Q from the nth flip-flop of the serially-connected flip-flops
210
-
1
-
210
-
n
to each flip-flop
210
-
1
-
210
-
n
, the feedback circuit can be configured to feedback to any number of the flip-flops
210
-
1
-
210
-
n
. However, since the generic MISR
200
compresses the signal on every clock cycle, regardless of whether it is a valid bus cycle or not, the generic MISR
200
is vulnerable to X-states and circuit glitches. “X-states” are unknown and undefined processor states which can occur during processor execution of application programs as a result of, for example, uninitiated nodes, signal contention as a result of internal circuit conflicts, and/or circuit glitches. “Circuit glitches” can include, for example, errors, transients and/or unintelligible signals.
In
FIG. 2
, adders
230
-
1
-
230
-
n
, which are generally implemented as exclusive OR (XOR) gates without the carry function, can each include an input channel to receive a bit from an output signal from a device to be tested as an input signal. The received bit from the output signal is combined in the XOR gate with the feedback circuit output signal Q and a second output signal Q from the predecessor flip-flop in the sequence of the serially-connected flip-flops
210
-
1
-
210
-
n
−1. As
FIG. 2
illustrates, since the first XOR gate
230
-
1
does not have a predecessor flip-flop, the first XOR gate
230
-
1
only receives and combines the received output signal from the tested device and the feedback circuit output signal Q.
Unfortunately, since most current signature analyzers require full compliance with a specific design methodology, for example, Scan which requires no contention problems, these signature analyzers are unable to test the buses and integrated chip components that are not built according to the specific design methodology requirements.
Recently, a new structural test technique called Structural Based Functional Test (SBFT), which runs functional tests from embedded caches, has been developed. SBFT calls for the use of scanout nodes to capture internal data as well as bus data. However, since the scanout technique compresses data on every clock cycle, the signature is easily contaminated with X-states. Although these X-states may be benign in normal operations, they will cause the signature produced to be unreliable and thus unusable. As a result, to make the normal scanout signature compression solution work would require lengthy debug and extensive design fixes to overcome the X-state induced problems.
Unfortunately, since the current ATE systems are not capable of the same high speeds as the new chip and memory component designs, the current ATE systems can not be used to directly test these new high-speed integrated circuits. Similarly, since many new devices exceed the pin count capability of the current ATE systems, not all pins of these new devices can be connected to the ATEs and, thus, these high pin count devices can not be tested on the current ATE systems.
Therefore, a device and method are needed that will perform high speed functional testing of high-speed bus and integrated chip components and buses and integrated chip components with pin counts which exceed the capabilities of current test equipment and for integrated circuits and chips.


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