Bus performance evaluation method for algorithm description

Details Bus performance evaluation method for algorithm description Bus performance evaluation method for algorithm description

2008-04-29

2008-04-29

Thangavelu, K (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S014000, C703S022000, C716S030000, C716S030000, C716S030000, C716S030000, C714S030000, C714S043000

Reexamination Certificate

active

09872091

ABSTRACT:
The LSI design and development in manufacture is actualized by algorithm design, architecture design, actual hardware and software design, and verification. Herein, the architecture design contains a simulation program structuring process and a bus performance evaluation process, which are interconnected by a feedback loop. In the algorithm design, sources are described by the general-purpose high-level language such as the C language and C++ language. In the simulation program structuring process, the sources are subjected to isolation of the hardware and software, while an evaluation function is created to count bus traffic of the bus interconnecting the hardware and software. Every time data is written to a pre-defined variable loaded onto the bus, the evaluation function is performed to modify the sources. Then, evaluation is performed on the performance of the bus, so that the bus traffic for its processing rate is finally produced. That is, the result of the bus performance evaluation process is fed back to the simulation program structuring process such that isolation of the hardware and software is optimized in response to the bus traffic for the processing rate of the bus. This brings exclusion of feedback loops derived from the cooperative verification after the actual coding, so it is possible to considerably reduce overall turnaround time of design.

REFERENCES:
patent: 5604895 (1997-02-01), Raimi
patent: 5801958 (1998-09-01), Dangelo et al.
patent: 6212489 (2001-04-01), Klein et al.
patent: 6269467 (2001-07-01), Chang et al.
patent: 6321366 (2001-11-01), Tseng et al.
patent: 6510541 (2003-01-01), Fujiwara et al.
patent: 6546505 (2003-04-01), Swoboda et al.
patent: 6694488 (2004-02-01), Raghunathan et al.
Brage et al., “A codesign case study in computer graphics”, IEEE, 1994.
Vahid et al., “Toward a model for hardware and software functional partitioning”, IEEE, 1996.
Adams et al., “Execution time profiling for multiple process behavioral synthesis”, IEEE, 1995.
Lahiri et al., “Fast performance analysis of bus-based system-on-chip communication architectures”, IEEE, 1999.
Knudsen et al., “ Integration communication protocol selection with hardware/software codesign”, IEEE, 1999.
Ernst, R. et al., “Hardware-Software Cosynthesis for Microcontrollers”, IEEE Design & Test of Computers, IEEE, US, vol. 10, No. 4; pp. 64+65-75, Dec. 1, 1993.
Temam, O. et al., “Software Assistance for Data Caches”, Future Generation Computer Systems, Elsevier Science Publishers, NI, vol. 11, No. 6, Oct. 1, 1995; pp. 519-536.
Herrman, D. et al., “An Approach to the Adaptation of Estimated Cost Parameters in the COSYMA System”, Hardware/Software Codesign, 1994; Proceedings of the Third International Workshop on Grenoble, France, Sep. 22-24, 1994 , pp. 100-107.
Cosyma Architecture and Input Languages, “Online”, Oct. 15, 1998 XP002230336.
European Examination Report dated Jul. 10, 2003.
Japanese Office Action dated Sep. 7, 2004.
Kale Tammermāe, et al. “AKKA: A tool-Kit for Cosynthesis and Prototyping”, IEE Digest-Colloquim on Hardware-Software Cosynthesis for Reconfigurable Syhstems, vol. 96, No. 036, Feb. 1996 pop./ 8/a-8/8, XP0002244550.
o'Nils, M. et al.Interactive Hardware-Software Partitioning and Memory Allocation Based on Data Transfer Profiling, Int. Conf. Recent Adv. in Mechatronics. (1) Aug. 14, 1995, 447-452.

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