1996-03-04
1998-03-17
DeCady, Albert
G06F 1100
Patent
active
057296782
ABSTRACT:
A bus monitor system comprises eight identical programmable monitor circuits that are each connected to a monitored bus and to a local 16-bit event bus. There are three interfaces to the event bus within each monitor circuit. One interface asserts a predetermined bit pattern on the event bus when match conditions occur between bit patterns on the monitored bus and predetermined bit patterns stored in monitor circuit registers. A second interface asserts a signal on an external pin when bit patterns on the event bus match a predetermined bit pattern stored in a monitor circuit register. A third interface asserts a predetermined bit pattern on the event bus when an external device has asserted a signal on an external pin. Each monitor circuit is capable of reading and asserting any of the bits of the event bus. The event bus is used to enable or disable monitor circuit interfaces. If any asserted bit on the event bus matches a corresponding bit of one of the predetermined bit patterns stored in the interface enable and disable registers, that interface will be enabled or disabled, respectively. The event bus gives the monitor system the ability to simultaneously monitor for multiple bit patterns on the monitored bus, and to monitor for a sequence of bit patterns by having one monitor circuit trigger another.
REFERENCES:
patent: 4453211 (1984-06-01), Askinazi et al.
patent: 5426741 (1995-06-01), Butts, Jr. et al.
patent: 5471462 (1995-11-01), Amador
Brown Randall Lew
Gilbert Michael
Hunt Jeffrey Glenn
Perry Thomas Jay
Southway, Jr. James B.
AG Communication Systems Corporation
De'cady Albert
Hendricks Gregory G.
Zwick David J.
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