Bus master having burst transfer mode

Details Bus master having burst transfer mode Bus master having burst transfer mode

1986-09-18

1989-01-17

Hecker, Stuart N.

Static information storage and retrieval

Addressing

365235, 365238, G11C 800, G11C 1140

Patent

active

047991992

ABSTRACT:
A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address provided by the bus master, where m is two (2) to the n power, n being an integer and characteristic of the memory. The bus master is adapted to automatically increment, modulo m, a selected set n of the bits of the access address as each operand in the burst is transferred, provided that the memory has indicated that the burst can be continued and less than m operands have been transferred.

REFERENCES:
patent: 4236203 (1980-11-01), Curley et al.
patent: 4370712 (1983-01-01), Johnson et al.
patent: 4633441 (1986-12-01), Ishimoto
The Handbook of Microcomputer Interfacing by Steve Leibson Tab Book Inc., Pa. 1983 pps. 90-105; 127-133.

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