Bus master arbitration circuitry having improved prioritization

Details Bus master arbitration circuitry having improved prioritization Bus master arbitration circuitry having improved prioritization

1996-08-05

1998-08-18

Sheikh, Ayaz R.

395287, G06F 1314

Patent

active

057970203

ABSTRACT:
An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

REFERENCES:
patent: 4423384 (1983-12-01), DeBock
patent: 4602327 (1986-07-01), Laviolette et al.
patent: 4663756 (1987-05-01), Retterath
patent: 4706190 (1987-11-01), Bomba et al.
patent: 4755938 (1988-07-01), Takahashi et al.
patent: 4764862 (1988-08-01), Barlow et al.
patent: 4941086 (1990-07-01), Kriz
patent: 4980854 (1990-12-01), Donaldson et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 5067071 (1991-11-01), Schanin et al.
patent: 5068781 (1991-11-01), Gillett, Jr. et al.
patent: 5109491 (1992-04-01), Nakagawa et al.
patent: 5127089 (1992-06-01), Gay et al.
patent: 5167022 (1992-11-01), Bahr et al.
patent: 5253347 (1993-10-01), Bagnoli et al.
patent: 5265223 (1993-11-01), Brockmann et al.
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5339443 (1994-08-01), Lockwood
patent: 5363492 (1994-11-01), King et al.
patent: 5546548 (1996-08-01), Chen et al.
patent: 5555425 (1996-09-01), Zeller et al.
IBM Technical Disclosure Bulletin, vol. 34, No. 2, Jul. 1991, "Shared Memory Design with Input and Output Queues", pp. 400-403.
Patent Abstracts of Japan, vol. 16, No. 520 (P-1444), Oct. 26, 1992 & JP-A-04 192056 (Fujitsu Ltd.) Jul. 10, 1992, Abstract Only.
82420/82430 PCI Set, Isa and EISA Bridges, Intel Corp., pp. 3-5, 17, 35, 37, 148, 154-157, 172-174, 211, 225-226, 293-302, 320-321, 345, 363-364, 438-444, 460-462 (1993).

Affiliated with

Also associated with

Rating

Bus master arbitration circuitry having improved prioritization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus master arbitration circuitry having improved prioritization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus master arbitration circuitry having improved prioritization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1125267