Bus-line drive circuit and semiconductor storage device comprisi

Details Bus-line drive circuit and semiconductor storage device comprisi Bus-line drive circuit and semiconductor storage device comprisi

1996-12-18

1998-09-15

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365194, G11C 800

Patent

active

058089560

ABSTRACT:
A bus-line drive circuit comprises an inverter INV1 formed of a PMOS transistor Q1 and an NMOS transistor Q2 having gates to which internal read data d.sub.o is input, a delay circuit DL that receives an output signal from the inverter INV1, a PMOS transistor Q7 and an NMOS transistor Q8 that receive an output signal from the inverter INV1, and a depletion-mode NMOS transistor DQ1 that receives an output from the delay circuit DL. When the level of the internal read data d.sub.o goes high, the signal potential applied to the gate of the depletion-mode NMOS transistor DQ1 remains high, so that the bus line L.sub.o can be charged by a large current supply capability. The bus line L.sub.o is subsequently discharged gradually by the delay circuit DL. This operation ensures that the potential of the bus line L.sub.o gradually falls to a fixed value which is less than the power supply voltage V.sub.DD and does not rise any further because the gate potential of the depletion-mode NMOS transistor DQ1 is made to be low by the delay circuit, thus enabling a lower power consumption, higher speeds, and a low voltage margin.

REFERENCES:
patent: 5442307 (1995-08-01), Shigehara et al.
"Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI's", Mitsuru Hiraki et al., IEEE Journal of Solid-Sate Circuits, Apr. 1995: vol. 30, No. 4, pp. 397-402.

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