Bus interface unit in a microprocessor for facilitating internal

Details Bus interface unit in a microprocessor for facilitating internal Bus interface unit in a microprocessor for facilitating internal

1997-02-21

1999-06-22

Sheikh, Ayaz R.

395309, 395872, G06F 1300

Patent

active

059150998

ABSTRACT:
In a microprocesssor (101), a selector (7) is connected to a bus ID <0:127> through a write buffer (5) and a DRAM (27), a cache (28) and an IQ (8) are also connected to the bus ID <0:127>. The bus ID <0:127> and the microprocessor (101) are connected to the external memory (4) and the external bus master (41) with a data bus D <0:15> through a BIU (3). The microprocessor (101) is also connected to the external memory (4) and the external bus master (41) with an address bus (58) and control bus (57). The BIU (3) controls an access to a memory integrated in the microprocessor (101) and a memory externally connected thereto. With this configuration, the DRAM and the cache can be integrated together in the microprocessor which is externally connected to the bus master.

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