Bus interface unit for preventing deadlock

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Details

395287, 395859, 395860, 395728, 395732, G06F 1314

Patent

active

059499800

ABSTRACT:
A bus interface unit has an arbitrating unit, in response to cycle requests received from internal devices of a processor and a resumption request, for determining an internal device having the highest priority and generating a cycle acknowledgment signal representing thereof; a queue input multiplexing unit, in response to the cycle acknowledgment signal, for selecting cycle queue data from the determined internal device to generate selected cycle queue data; a cycle queue storing unit for storing the selected cycle queue data and state information under; and a queue controlling unit for controlling the cycle queue storing unit to store the selected cycle queue data and the state information under the condition that a back-off condition occurs, and for resuming a cycle under the condition that the back-off condition is cleared by using the stored selected cycle queue data based on the state information to provide the resumption request to the arbitrating unit.

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patent: 5542079 (1996-07-01), Hatakeyama
patent: 5544332 (1996-08-01), Chen

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