Patent
1997-11-07
1999-03-09
Donaghue, Larry D.
395872, 39580023, 39580038, 39520064, 395391, 395821, G06F 1314
Patent
active
058812563
ABSTRACT:
A bus interface unit of a microprocessor which can simultaneously process bus cycle's requests coming from various pipelines during for one cycle in the pipelined high-performance microprocessor of a superscalar type. The bus interface unit includes a bus cycle arbiter for arbitrating a plurality of cycle requests inputted from a plurality of units, a cycle multiplexer for selecting cycle information inputted from the units in response to an arbitration determination of the bus cycle arbiter, a cycle queue for storing selected information, a cycle generator for generating a bus cycle in response to the information stored in the cycle queue, a bus controller for controlling the bus interface unit as a whole, and a write buffer for enabling a next operation without waiting for the core unit to complete its write operation to improve a performance of a memory write cycle. According to the bus interface unit, the bus cycle requests from respective pipelines of the microprocessor are simultaneously processed during one cycle.
REFERENCES:
patent: 5398244 (1995-03-01), Mathews et al.
patent: 5574937 (1996-11-01), Narain
Iacobovici et al., "Balanced Microprocessor Design Keeps Performance Peaked", IEEE, 1989, pp. 371-375.
Donaghue Larry D.
Follansbee John
Hyundai Electronics Industries Co,. Ltd.
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