Bus interface synchronization control system

Details Bus interface synchronization control system Bus interface synchronization control system

1989-09-12

1993-08-10

LaRoche, Eugene R.

G06F 112

Patent

active

052356981

ABSTRACT:
The interface control system of this invention renders a high speed CPU compatible with low speed expansion devices such as expansion interfaces. The system causes the CPU clock signal to be in phase with the interface clock signal at the end of the last cycle of an interface cycle. At the end of the interface cycle, the system selects between a positive high speed and a negative high speed clock to be the CPU clock signal applied to the CPU.

REFERENCES:
patent: 4095267 (1978-06-01), Morimoto
patent: 4241418 (1980-12-01), Stanley
patent: 4439829 (1984-03-01), Tsiang
patent: 4819164 (1989-04-01), Branson
patent: 5033001 (1991-07-01), Ibi
CS8221 New Enhanced at (NEAT.TM.) Data Box 82C211/82C212/82C215/82C206 (IPC) CHIPSet.TM., Pub. #2-221-B 10M, Mar. 1988, Rev. 2.

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