Bus interface synchronization circuitry for reducing time betwee

Details Bus interface synchronization circuitry for reducing time betwee Bus interface synchronization circuitry for reducing time betwee

1990-07-20

1994-01-04

Lee, Thomas C.

Boots, shoes, and leggings

395550, 364240, 3642401, 3642408, 3642409, 3642705, 364DIG1, 370 91, 3701001, G06F 1342

Patent

active

052768074

ABSTRACT:
Bus interfacing circuitry provides for high speed communication of signals on a bus by using circuitry that synchronizes data transfers to a single reference point, executes commands from a dual-ranked buffer in order to reduce time consumed by external interrupts, and stores multiple bytes in a FIFO buffer to allow rapid sequential transfers; while also providing a flexible input/output configuration allowing both single-ended and differential mode connections.

REFERENCES:
patent: 4390969 (1983-06-01), Hayes
patent: 4587609 (1986-05-01), Boudreau et al.
patent: 4807116 (1989-02-01), Katzman et al.
patent: 5014186 (1991-05-01), Chisholm
patent: 5133062 (1992-07-01), Joshi et al.

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