Bus interface device for a data processing system

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

364900, 307480, 3072471, H04L 700, G06F 1300

Patent

active

046481028

ABSTRACT:
A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines.
The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7.
The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.

REFERENCES:
patent: 4442502 (1984-04-01), Friend et al.
patent: 4481640 (1984-11-01), Chow et al.
patent: 4491909 (1985-01-01), Shimizn
patent: 4539533 (1985-09-01), French
patent: 4547738 (1985-10-01), Bayer et al.
Electro 76 Professional Program No. 1976, 1976, pp. 1-6, Session 20-3, New York, T. McMullen et al.: "Using Digital Techniques for Improved Weak Signal Reception".
Michael Rogers: "Locate Interrupts for .mu.p Peripherals Quickly Without the Need for Polling"; Electronic Design, vol. 25, No. 5, 7/1977, pp. 104-106.

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