Bus interface circuit for controlling data transfer

Details Bus interface circuit for controlling data transfer Bus interface circuit for controlling data transfer

1991-07-29

1994-09-06

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 364239, 3642391, 3642393, 3649261, 36492792, 36492793, G06F 1300

Patent

active

053455592

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a bus interface circuit and particularly to a bus interface circuit for controlling data transfer between buses in different bit width of the address lines and data lines.
2. Description of the related Art
In a computer system having a couple of buses, a bus interface is generally necessary between these buses. For instance, in the multiprocessor system, a plurality of central processing units (CPU), memories, and input/output units (I/O units) which are common resources of these CPUs respectively provide first buses and connect these buses through the common second bus. In general, the first bus is called a local bus and the second bus is called a system bus. The bus interface is provided, corresponding to each local bus, for connecting the corresponding local bus to the system bus.
A computer system in these years tends to increase the amount of information to be transferred (address and a series of data) in a single transfer sequence by widening the bus width in order to improve system performance.
However, when bus width is widened, a number of signal lines naturally increases and the scale of hardware becomes large. Therefore, considering the required performance of the system, the width of second bus (system bus) must be determined to be of N bits (for example, 32 bits) or of to 2N bits (for example, 64 bits).
Thereby, it is effective for the bus interface to have the structure ready for both N bits mode and 2N bits mode. The present invention relates to a bus interface which may be used in common for such N-bit/2N-bit (including 3,4, . . . mN-bit) widths.
FIG. 1 is a schematic diagram of the system example to which the present invention is applied. In FIG. 1, a computer system 10 comprises a plurality of first buses (local bus) 11 and a second bus (system bus) 12 as the buses for information transfer. The first bus 11 is connected with the central processing unit (CPU) 14, memory (MEM) 15 and I/O unit 16.
These first bus 11 and second bus 12 are connected through bus interface (BS I/F) 13. In this case, the second bus 12 has the width, for example, of 32 (N= 32) bits but it must be expanded up to 2N (=64) bits when improvement of system performance is requested. Accordingly, it is convenient that the bus interface 13 may be used in common to N bits and 2N bits.
FIG. 3 is a timing chart indicating the operations in the transmitting side of the system, particularly in the side of a first bus (N bits) in the prior art of FIG. 2. S111, S112 in FIG. 3 denote the switching control signals (selecting REG100 or REG101) applied to the selector 110 of FIG. 2.
FIG. 4 is a timing chart indicating operations in the transmitting side of the system and particularly in the side of second bus (N bits) in the prior art of FIG. 2. S121, S122 in FIG. 4 denote the switching control signals (selecting REG102 or buffer 21) applied to the selector 120 of FIG. 2.
FIG. 5 is a timing chart indicating operations in the transmitting side of the system and particularly in the side of the second bus (2N bits) in the prior art of FIG. 2. S131, S132 in FIG. 5 denote the switching control signals (selecting REG105 or REG106) applied to the selector 130 in FIG. 2.
FIG. 6 is a timing chart indicating operations in the receiving side of the system and particularly in the side of the second bus (N bits) in the prior art of FIG. 2. S131, S132 in FIG. 6 denote the switching control signals (selecting REG105 or REG106) applied to the selector 130 in FIG. 2.
FIG. 7 is a timing chart indicating operations in the receiving side, particularly in the side of the second bus (2N bits) in the prior art of FIG. 7.
FIG. 8 is a timing chart indicating operations in the receiving system, particularly in the side of the first bus in the prior art of FIG. 2.
According to the bus interface of the prior art, when the second bus (system bus) 12 changes to 2N bits mode (FIG. 5) from the N bits mode (FIG. 4), a problem arises that the read cycle of buffer must be reduced

REFERENCES:
patent: 5220651 (1993-06-01), Larson
patent: 5224213 (1993-06-01), Dieffenderfer et al.

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