Bus interconnect circuit including port control logic for a mult

Details Bus interconnect circuit including port control logic for a mult Bus interconnect circuit including port control logic for a mult

1993-03-05

1996-01-16

Chin, Wellington

Multiplex communications

Wide area network

Packet switching

370 943, 370 8513, H04L 12413, H04L 1244

Patent

active

054854580

ABSTRACT:
A bus interconnect device including port control logic for a communication network having a plurality of multi-port nodes that are connected with point-to-point links. Each node includes a transceiver, turn around logic that controls the transceiver, and a dominant logic physical bus that is coupled to all ports in a node. A bus interconnect device includes a first port, a second port, and a point-to-point link between the first and second ports. During arbitration, from the viewpoint of each node, the bus interconnect devices cause the plurality of physical buses to appear to be a single logical bus having a dominant logic. During data transfer following arbitration, the bus interconnect devices are configured to transmit data from the winning node to all other nodes.

REFERENCES:
patent: 4349870 (1982-09-01), Shaw et al.
patent: 4707827 (1987-11-01), Bione et al.
patent: 4719458 (1988-01-01), Miesterfeld et al.
patent: 4897784 (1990-01-01), Nay
patent: 4897841 (1990-01-01), Gang, Jr.
patent: 4985892 (1991-01-01), Camarata
patent: 5073982 (1991-12-01), Viola et al.
patent: 5107257 (1992-04-01), Fukuda
patent: 5119398 (1992-06-01), Webber
patent: 5200743 (1993-04-01), St. Martin et al.
patent: 5249183 (1993-09-01), Wong et al.
patent: 5311114 (1994-05-01), Sambamurthy et al.
patent: 5339307 (1994-08-01), Curtis
P1394 Working Group of the Microprocessor and Microcomputer Standards Committee, "High Performance Serial Bus", The Institute of Electrical and Electronic Engineers, Inc., Draft 4.2, Nov. 6, 1991.
P1394 Working Group of the Microprocessor and Microcomputer Standards Committee, "High Performance Serial Bus", The Institute of Electrical and Electronic Engineers, Inc., Draft 5.0v1, Mar. 8, 1992.
P1394 Working Group of the Microprocessor and Microcomputer Standards Committee, "High Performance Serial Bus", The Institute of Electrical and Electronic Engineers, Inc., Draft 5.3v1, Oct. 14, 1992.
James, David. V., "Scalable I/O Architecture for Buses," IEEE, 1989, pp. 539-544.
Teener, Michael, "A Bus on a Diet-The Serial Bus Alternative-An Introduction to the P1394 High Performance Serial Bus", IEEE, 1992, pp. 316-321.
Hewlett Packard Journal, vol. 38, No. 6, Jun. 1987, Palo Alto, pp. 8-12, "The Hewlett Packard Human Interface Link".

Affiliated with

Also associated with

Rating

Bus interconnect circuit including port control logic for a mult does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus interconnect circuit including port control logic for a mult, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus interconnect circuit including port control logic for a mult will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-314882