Bus grant circuit

Details Bus grant circuit Bus grant circuit

1983-08-18

1986-09-09

Thomas, James D.

Boots, shoes, and leggings

G06F 1314

Patent

active

046112979

ABSTRACT:
A bus grant circuit for controlling access by a digital device connected to a common bi-directional bus and a bus arbitration system incorporating such circuit. The bus arbitration system comprises a common bus request, a common bus busy line, a bus grant line daisy-chained through each device which may request bus control and a bus arbitrator which asserts a signal on the bus grant line in response to a bus request signal and the absence of a bus busy. Each device which may request bus control includes an associated bus grant circuit comprising a first flip-flop responsive to the input of the bus grant signal and to an internal bus request signal from the associated device to set when the bus grant signal is asserted and the internal bus request signal is not asserted, allowing the bus grant signal to be passed on, a second flip-flop responsive to the input of the bus grant signal and to the internal bus request signal to set when the bus grant signal and the internal bus request signal are asserted, allowing the associated device to the control of the bus, and associated logic for preventing both circuits from being set simultaneously.

REFERENCES:
patent: 4275440 (1981-06-01), Adams, Jr. et al.
patent: 4365294 (1982-12-01), Stokken et al.
patent: 4415972 (1983-11-01), Adcock
patent: 4454581 (1984-06-01), Nystrom
patent: 4471425 (1984-09-01), Yamaguchi et al.
patent: 4539656 (1985-09-01), Abrant
"High Speed Bus Arbiter for Bus-Oriented Multiprocessor Systems", IBM Technical Disclosure Bulletin, vol. 28, No. 2, 7/85, pp. 567-569.

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