Bus expander with logic for virtualizing single cache control in

Details Bus expander with logic for virtualizing single cache control in Bus expander with logic for virtualizing single cache control in

1986-07-29

1989-08-01

Williams, Jr., Archie E.

Boots, shoes, and leggings

36424341, 36424344, 364240, 3642405, G06F 1200, G06F 1202, G06F 1208, G06F 1212

Patent

active

048538469

ABSTRACT:
Control logic for controlling references to a cache (24) including a cache directory (62) which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory (62) for cache data-array addresses. A cache-configuration register and control logic (64) splits the cache directory (62) into two logical directories, one directory for controlling requests from a first processor and the other directory for controlling requests from a second processor. A prefetch buffer (63) is provided along with a prefetch control register for splitting the prefetch buffer into two logical channels, a first channel for handling prefetches associated with requests from the first processor, and a second channel for handling prefetches associated with requests from the second processor.

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patent: 4400770 (1983-08-01), Chan et al.
patent: 4445174 (1984-04-01), Fletcher
patent: 4484267 (1984-11-01), Fletcher
patent: 4533995 (1985-08-01), Christian et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4736293 (1988-04-01), Patrick

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