Excavating
Patent
1989-02-10
1990-08-07
Smith, Jerry
Excavating
371 226, G01R 3128
Patent
active
049473956
ABSTRACT:
For LSI/VLSI integrated circuits which inherently have an address decoder and a data bus, a scan testing method and apparatus is presented which does not require additional pin connections to be dedicated for scan test implementation. Counter to the Joint Test Action Group approach, the present invention uses additional registers, multiplexers, and decoders in conjunction with the existing buses to provide test access to otherwise embedded layers of logic circuitry, without the addition of a single pin connection to a integrated circuit chip package. Further, since this test method and apparatus uses the data bus and registers just as the rest of the chip, slow and complex d.c. level shifting equipment is not required.
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Bullinger Philip W.
Langford, II Thomas L.
Stewart John W.
Beausoliel Robert W.
Hawk Jr. Wilbert
Jewett Stephen F.
NCR Corporation
Penrod Jack R.
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