Bus error recognition for microprogrammed data processor

Details Bus error recognition for microprogrammed data processor Bus error recognition for microprogrammed data processor

1980-04-03

1982-09-07

Shaw, Gareth B.

Boots, shoes, and leggings

371 32, G06F 1100, H04L 100

Patent

active

043487220

ABSTRACT:
An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage means is reset. If, however, a halt signal accompanies the bus error signal, the storage means is not reset and the bus cycle is rerun when the halt signal terminates.

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Birney and Nielsen, "Save Storage Address on Error Class Interrupts", IBM Tech. Discl. Bull., vol. 19, No. 11, Apr. 77, pp. 4062-4068.

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