Bus error processing system having direct bus master/CPU communi

Details Bus error processing system having direct bus master/CPU communi Bus error processing system having direct bus master/CPU communi

1991-10-11

1994-12-20

Shaw, Gareth D.

Boots, shoes, and leggings

364DIG1, 3642328, 3642412, 36424292, 3642653, 3642808, G06F 1332

Patent

active

053752112

ABSTRACT:
A bus error ascribable to a bus master module other than a central processing unit (CPU) is set as a specified factor for an exception process. When the exception process is requested, the CPU carries a corresponding service program for the exception process into execution without executing a process for altering and setting mask bits as is executed for an interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by the interrupt request etc. accepted before the bus error, and besides, a period of time which is expended before the start of the run of a service program corresponding to the bus error is shortened, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module other than the CPU is enhanced.

REFERENCES:
patent: 4727477 (1988-02-01), Gavril
MC68020 32-Bit Microprocessor User's Manual by Motorola Inc., 1984, pp. 5-42-5-46, 6-5-6-16, 8-3, 8-12, 8-13, 8-25-8-34.
CMOS 16-Bit MPU and DMAC, Y. Suzuki, et al., Hitachi Review, vol. 35, No. 5, Oct. 1986, pp. 241-246.
The SCC68070: a monolithic 68000 CPU and peripherals, G. Conn, Electronic Components & Application, vol. 8, No. 2, 1987, pp. 95-100.
Motorola M68000 8-/16-/32-Bit Microprocessor User's Manual, seventh edition, pp. 5-1-6-9.
Signetics, SCC68070, objective specification, p. 10, published Dec., 1985.

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