Bus error handler for PERR# and SERR# on dual PCI bus system

Details Bus error handler for PERR# and SERR# on dual PCI bus system Bus error handler for PERR# and SERR# on dual PCI bus system

1995-12-15

1998-08-04

Sheikh, Ayaz R.

395308, G06F 1324

Patent

active

057908702

ABSTRACT:
An apparatus for handling bus error signals is provided for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR# signals, and a second PCI bus with second PERR# and SERR# signals. The apparatus has a buffer with an input connected to ground, an enable input connected to the second SERR# signal, and an output connected to the first SERR# signal. When the second SERR# signal is asserted, the first SERR# signal is also asserted via the buffer and is provided to one input of the interrupt controller. In an alternate embodiment, the buffer enable input is connected to the first SERR# signal and the buffer output connected to the second SERR# signal. The apparatus also receives the first and second PERR# signals and logically ORs the signals together to generate a combined PERR# signal. The combined PERR# signal is presented to a register which is clocked by the PCI system clock to synchronize the combined PERR# signal to the PCI clock before presenting the PERR# signal to a second input of the interrupt controller. The interrupt controller generates an interrupt to the processor and causes the processor to poll devices to identify the board that might have caused the error and to take a corrective action.

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PCI Local Bus Specification Revision 21 Jun. 1, 1995.
PCI Local Bus Specification, Production Version, Revision 2.0, (Apr. 30, 1993) .COPYRGT.1992, 1993 PCI Special Interest Group.

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