Bus error detection employing parity verification

Details Bus error detection employing parity verification Bus error detection employing parity verification

1987-11-16

1989-04-25

Atkinson, Charles E.

Excavating

371 49, G06F 1110

Patent

active

048254380

ABSTRACT:
A bus error detection system is used to detect binary bus error signals. The bus lines include an odd parity line and an even parity line. A clock means provides at least two clock signal phases. An activatable driver drives both of the odd and the even parity lines to the same predefined logic level each time a first clock signal phase occurs. A parity checker coupled to the drive checks during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase. The driver then drives either the odd or the even parity lines to a predefined logic state according to the parity determined by the parity checker during the second clock signal phase. A verification circuit verifies that only one of the odd and the even parity lines has been driven to a predefined logic state during said second clock phase, and that of both the odd and the even parity lines have been driven during said first clock signal phase to the same predefined logic level.

REFERENCES:
patent: 3102253 (1963-08-01), Blodgett
patent: 4119815 (1978-10-01), Frankfort et al.
patent: 4346474 (1982-08-01), Sze
patent: 4365247 (1982-12-01), Bargeton et al.

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