Bus driving and decoding circuit

Details Bus driving and decoding circuit Bus driving and decoding circuit

1988-08-10

1990-10-30

Heckler, Thomas M.

Boots, shoes, and leggings

3649428, 3649471, 36493542, G06F 300

Patent

active

049673904

ABSTRACT:
Bus driving and decoding circuit for validating the decoding of signals put on the bus by said drivers, comprising a plurality of driver elements and a decoder connected to the bus, the drivers being grouped in at least two sets, each implemented in one integrated component having a control input for enabling the opening of the related driver set, the control input receiving an enabling signal which is further input to one driver in each integrated component, so as to obtain at the output of the one driver a validation signal (V1, V2) for the decoder, each validation signal having an intrinsic delay equal to the propagation delay of the related integrated component, the circuit comprising further a delay element, located upstream or downstream of driver elements which generate the validation signals, to provide each of the validation signals with an incremental delay sufficing to cover the propagation delay spread specific to the related integrated component, the decoder being enabled by the joint assertion of the validation signals.

REFERENCES:
patent: 4376982 (1983-03-01), Bantz et al.
patent: 4453229 (1984-06-01), Schaire
patent: 4583193 (1986-04-01), Kraft et al.
"Customized Clock-Based Logic Design", IBM Tech. Discl. Bull., vol. 28, No. 6, Nov. '85, pp. 2623-2624.
Tetrick, R. S., "System-Level Metastability Considerations", Electro/87 and Mini/Micro Northeast, vol. 12, 1987, 3/2, pp. 1-9.

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