Bus driver circuit for high-speed data transmission

Details Bus driver circuit for high-speed data transmission Bus driver circuit for high-speed data transmission

1994-10-17

1996-12-31

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327288, 327404, 327108, H03H 1126

Patent

active

055897894

ABSTRACT:
A bus driver circuit includes a plurality of first MOS transistors connected in series between a data input terminal and a data output terminal, and a plurality of second controlling MOS transistors. Sources of said plurality of first MOS transistors are connected to drains of said plurality of second controlling MOS transistors. Also, gates of said plurality of second controlling MOS transistors to control signal source means for selectively turning ON and OFF said plurality of second controlling MOS transistors. The bus driver circuit thus constructed permits selection of optimal rise-up and fall-down transition period for achieving high speed and efficient data transmission.

REFERENCES:
patent: 4490626 (1984-12-01), Carlson
patent: 4914319 (1990-08-01), Hashimoto
patent: 5220216 (1993-06-01), Woo
patent: 5319258 (1994-06-01), Ruetz

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