Bus delay compensation circuitry

Details Bus delay compensation circuitry Bus delay compensation circuitry

1997-01-08

1999-04-06

Ray, Gopal C.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Converting, per se, of an ac input to corresponding dc at an...

395285, 395552, 327153, G06F 1300, H03K 5159

Patent

active

058929274

ABSTRACT:
Programmable delay compensation for interfacing transceiver with a micro-controller. The total propagation delay in transmitting a symbol across the transceiver and receiving an echo back from the transceiver is programmed by a user or software. Depending upon the protocol used in interfacing and symbol transmission, the total propagation delay, which is stored in a programmable register, is subtracted from prespecified symbol timings so that when the propagation delay is accounted for, the symbols, when echoed, will in reality, match the timings as prespecified by the protocol, so that successive symbols are timed appropriately.

REFERENCES:
patent: 3611435 (1971-10-01), Cooper
patent: 3665100 (1972-05-01), Pinkham
patent: 4928000 (1990-05-01), Eglise et al.
patent: 5241429 (1993-08-01), Holsinger
patent: 5475690 (1995-12-01), Burns et al.
patent: 5574866 (1996-11-01), Smith et al.

Affiliated with

Also associated with

Rating

Bus delay compensation circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus delay compensation circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus delay compensation circuitry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1379608