Bus data transmission verification system

Details Bus data transmission verification system Bus data transmission verification system

1988-09-13

1990-10-09

Atkinson, Charles E.

Excavating

371 3, G06F 1110

Patent

active

049625012

ABSTRACT:
A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.

REFERENCES:
patent: 4414669 (1983-11-01), Heckelman et al.
patent: 4670876 (1987-06-01), Kirk

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