Bus coupler between a system bus and a local bus in a...

Details Bus coupler between a system bus and a local bus in a... Bus coupler between a system bus and a local bus in a...

1998-12-14

2001-09-25

Grant, William (Department: 2121)

Data processing: generic control systems or specific application

Generic control system, apparatus or process

Plural processors

C711S141000, C711S146000

Reexamination Certificate

active

06295477

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The method and system of the present invention relate to the organization of multicomputer systems having a system bus which is common to a number of modules as well as additional bus systems which are local to the modules.
2. Description of the Prior Art
To improve system performance, multicomputer systems have buffer memories linked to each processor, usually called caches. To simplify programming, various measures, called cache coherence for example as described in the book “Computer Architecture—A Quantitative Approach” by J. L. Hennessy and D. A. Patterson, San Francisco 1995, are taken to ensure that, despite the data copies in the buffer memories, the entire memory of the multicomputer system is accessed uniformly and consistently at any time.
In such multicomputer systems, which a hierarchy of bus systems, it is expedient to have additional intermediate stores (registers) for individual cache lines. These registers may conflict with the cache contents, however. In particular, the case in which data in a write register has to be transferred to the system bus, like data from an intervention register, demands appropriate circuitry for both registers.
Accordingly, an object of the present invention is to reduce the outlay for dealing with such conflicts.
SUMMARY OF THE INVENTION
This object is achieved in a method and system wherein the data from the write register is transferred not directly, but indirectly, to the system bus via the local bus and the intervention register. Consequently, the outlay is reduced in that the write register supplies the data via the local bus to the intervention register in the same way as the processors so that the intervention register cannot discern any difference.
Accordingly, in an embodiment of the present invention, a system is provided for operating a coherence protocol for buffer memories which covers interventions in multiprocessor data processing units, wherein the system includes: a plurality of processors, each processor having a buffer memory containing a buffer line; at least one local bus connected to the plurality of processors; a system bus; a bus coupler connecting the system bus to the at least one local bus wherein the coherence protocol is mapped from the system bus onto the at least one local bus, the bus coupler including at least one intervention register and at least one write register which are both connected to the at least one local bus for read access and which are both connected to the system bus for write access, the at least one intervention register further including a device for subblock interchange; and wherein the at least one write register is particularly connected to the at least one local bus such that, where an intervention relates to content of the at least one write register, the content can be transferred via the at least one local bus to the at least one intervention register.
In another embodiment of the present invention, a method is provided for operating a coherence protocol for buffer memories which covers interventions in multiprocessor data processing units, wherein the method includes the steps of: mapping the coherence protocol from a system bus onto a local bus via a bus coupler, wherein the local bus is connected to processors which respectively have buffer memories containing buffer lines; transferring the buffer lines from the respective buffer memories to an intervention register in the bus coupler via the local bus at the instigation of the bus coupler; transferring the buffer lines from the intervention register to the system bus; writing a first buffer line to a write register in the bus coupler via a buffer memory at the instigation of the respective processor wherein it is specified that the first buffer line is to be transferred via the system bus to a main memory; providing the intervention register with a device for subblock interchange; and transferring the first buffer line from the write register to the intervention register via the local bus in the event that a request is made via the system bus for a buffer line which is in the write register.
Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and the Drawings.


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Scalable Shred-Memory Multiprocessor Architectures, Thakkar, et al., pp. 71-74.
Computer Architecture A Quantitative Approach, Patterson, et al., pp. 654-721.

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