Bus controller and electronic device in a system in which severa

Details Bus controller and electronic device in a system in which severa Bus controller and electronic device in a system in which severa

1994-11-16

1997-07-01

Teska, Kevin J.

Boots, shoes, and leggings

395292, 39520006, 364DIG1, 3642422, G06F 1314

Patent

active

056447540

ABSTRACT:
A bus controller for an electronic device which has an intelligence (or processor) of its own and a memory having a plurality of individually addressable memory locations which are connected with each other via a system bus. The bus controller can be connected with at least the memory and a network bus. The network bus serves for networking several electronic devices with each other (including the electronic device). The bus controller manages at least one request-receipt queue with queue elements for requests to be received over the network bus, wherein the queue is organized as a double-linked list.

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"A Cache Coherency Scheme for an Asynchronous Packet-Switched Shared Memory Multiprocessor", by S. Alles and S. Mahmud, Circuits and Systems, 1993 IEEE Midwest Symposium, pp. 173-176.
"On the Doubly-Linked List Protocol for Distributed Shared Memory Multiprocessor Systems", A. Lau et al., IEEE, Algorithms and Architecture, 1995 Int'l. Conference (1st), Feb. 1995, pp. 293-302.

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