Bus controller

Details Bus controller Bus controller

1992-06-02

1996-06-11

Harvey, Jack B.

395287, 395730, G06F 13368

Patent

active

055264948

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This invention relates to a bus controller.


BACKGROUND ART

The operation speeds of microcomputer's semiconductor circuits, which includes processing units, a main storage, and an I/O interface have improved in recent years. These processing units are connected to one another through a bus. Bus access speed sometimes limits the performance of the processing units when the processing units frequently access the main storage and I/O interface through the bus.
FIG. 1 is a timing chart showing a bus control system according to the prior art.
In the figure, one processing unit provides a data access request for accessing another processing unit that may be a main storage. An internal bus access signal is changed from a high logic to a low logic, and according to this change, an access request signal (HREQ#) is asserted. Here, the mark "#" indicates that the signal is active low.
The signal HREQ# is sent to, for example, an arbiter circuit that arbitrates a bus right. If the bus right is free, the arbiter circuit provides a bus right acquisition acknowledge signal (HACK#).
Upon receiving the signal HACK#, the processing unit becomes a bus master having the bus right to access the main storage to write and read data.
When the signal HREQ# is negated, the arbiter circuit recognizes this and negates the signal HACK# to release the bus right.
Transferring the two signals (HREQ# and HACK#) is called "bus arbitration."
This kind of conventional bus control system carries out the bus arbitration whenever a bus request is raised, so that, when the bus request is repeatedly issued, a bus access wait time is prolonged to deteriorate processing performance.
The bus access wait time is a time from asserting the signal HREQ# to receiving the asserted HACK# (a time ta in FIG. 1) and a time from providing a bus request to asserting the signal HREQ# (a time tb in FIG. 1).
A wait time Et accompanied by a single bus request is expressed as follows:
A wait time .SIGMA.tn for n times of bus requests is expressed as follows:
Namely, as the number of bus requests increases, the wait time becomes longer. This may hinder the performance of a processing unit, i.e., a bus request source that frequently accesses the storage means.
FIG. 2 shows two processing units (A and B) sharing a memory 10 through a common bus 1. When the processing unit B frequently accesses the memory, the efficiency of the system as a whole may deteriorate because the bus arbitration takes a long time.
An object of the invention is to reduce the bus access wait time and improve the performance of a processing unit, i.e., a bus request source that frequently accesses a storage means.


SUMMARY OF THE INVENTION

To achieve the object, the invention provides a bus controller used for a processing system having a plurality of processing units, a bus, and storage unit accessed by the processing units through the bus. At least some of the processing units have at least one of the bus controller forming unit such as a bus right request signal generation unit for providing a bus right request signal to another processing unit, bus access unit for accessing the bus after receiving a bus right acquisition acknowledgement, hold instruction units for generating a hold signal for holding the acquired bus right, bus right arbitration unit for arbitrating bus right request signals from the processing unit and notifying the processing unit of a result of the arbitration, and bus right release signal generation unit for generating a release signal to release the bus right acquired by the processing unit.
Based on this basic technical configuration, the bus controller comprises a request signal generation unit for generating a bus request signal in a given bus request source (one processing unit), bus right arbitration unit for arbitrating a bus right in response to the bus request signal and imparting the result of the arbitration bus access unit for accessing upon receiving a bus right acquisition acknowledgement; the bus with the bus request source (the process

REFERENCES:
patent: 4908749 (1990-03-01), Marshall et al.
patent: 5129090 (1992-07-01), Bland et al.
patent: 5140680 (1992-08-01), Best
patent: 5167022 (1992-11-01), Bahr et al.
patent: 5237696 (1993-08-01), Best
patent: 5301282 (1994-04-01), Amini et al.

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