Bus control system in a multi-processor system

Details Bus control system in a multi-processor system Bus control system in a multi-processor system

1993-08-23

1996-06-11

Ray, Gopal C.

Boots, shoes, and leggings

395293, 395280, 39520002, 39520006, 364240, 3642402, 3642403, 3642426, 36424292, 364DIG1, G06F 1342, G06F 1336, G06F 1300, G06F 1516

Patent

active

055264956

ABSTRACT:
A bus arbiter permits an answer transfer request to utilize a system bus with higher priority than a command transfer request, thereby increasing the processing efficiency of CPU boards. A multi-processor system utilize the system bus with a time split transfer system in which the data width of a unit is inserted into a command and an answer transmitted and received between processors and transmitted as bus width information, thus making it possible to interconnect a unit, which processes data of an arbitrary data width, to the system bus. Local memories of a plurality of units connected to the system bus can be accessed via a bus interface of an input and output unit.

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