Bus control system for arbitrating requests with predetermined o

Details Bus control system for arbitrating requests with predetermined o Bus control system for arbitrating requests with predetermined o

1992-02-24

1993-03-09

Lee, Thomas C.

Boots, shoes, and leggings

36424292, 3642428, 3642405, 3642703, 3642715, 3649342, 3649370, 36492691, 364DIG1, 364DIG2, 3408255, 370 852, 370 856, 395550, G06F 1336, G06F 13372

Patent

active

051931931

ABSTRACT:
A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

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