Bus control preemption logic

Details Bus control preemption logic Bus control preemption logic

1992-06-22

1995-02-21

Richardson, Robert L.

Boots, shoes, and leggings

3642426, 36424293, 364DIG1, G06F 1300

Patent

active

053924045

ABSTRACT:
A method and system for monitoring and controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least first and second input/output devices each having a coprocessor incorporated therein. The system bus electrically interconnects the system devices and system memory. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. In addition, the memory controller may serve as a bus master on behalf of a slave device requesting access to the system bus. The input/output devices have control logic incorporated therein for (i) determining when an alternate input/output device requests control of the bus, (ii) outputting a preemption signal in response to the alternate request, and (iii) relinquishing control of the bus in response to the preemption signal.

REFERENCES:
patent: 4787082 (1988-11-01), Delaney
patent: 5163143 (1992-11-01), Culley et al.

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