Bus control method and apparatus

Details Bus control method and apparatus Bus control method and apparatus

1983-09-07

1987-02-03

Eng, David Y.

Boots, shoes, and leggings

G06F 1314, G06F 1340

Patent

active

046412379

ABSTRACT:
A bus control method and apparatus wherein buses each coupling a pair of processors are serially arranged rectilinearly into a cluster bus which is arranged in one direction and wherein a plurality of such cluster buses are arranged in a plurality of directions as a lattice pattern to form a multiprocessor system. Each of the processors supplies the respective cluster buses with send request and priority processing level signals and receives a receipt acknowledge signal from another processor on the same cluster bus, thereby to occupy said cluster bus, so as to transfer data to the other processor on the cluster bus.

REFERENCES:
patent: 4320452 (1982-03-01), Kempf et al.
patent: 4384327 (1983-05-01), Conway et al.
patent: 4390944 (1983-06-01), Quackenbush
patent: 4511959 (1985-04-01), Nicolas et al.

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