Bus control for a plurality of digital signal processors connect

Details Bus control for a plurality of digital signal processors connect Bus control for a plurality of digital signal processors connect

1993-11-15

1996-01-02

Lim, Krisna

Boots, shoes, and leggings

364DIG1, 36424291, 36425292, 3642405, 395478, 395732, G06F 1314, G06F 1316

Patent

active

054817277

ABSTRACT:
A multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) connected in parallel, each DMM having a DSP, a local memory and an interrupt control unit, a plurality of common memories for storing data which is being processed, parameters, etc., an input frame memory which enables reading and writing operations to be executed asynchronously, a combination of a task control unit and a task table for distributing tasks to the DMM's, a plurality of independent common buses, and a combination of a bus control unit and a bus control table for bus sharing control.

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