Bus control device for computer system having computer and DMA d

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364240, 3642405, 36424231, 36424292, 364DIG1, G06F 1300

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active

057457077

ABSTRACT:
In a bus control device for DMA processing/external master transfer which is carried out by a personal computer having a write back cache, a route having a high-speed buffer inserted between a data bus for peripherals and a host data bus is separately provided, data which are written back (copied) into a main memory through a write-back operation which is required when a cache memory is dirty-hit at a read-access time of a DMA device into a cache area of the main memory are also supplied to and stored in the high-speed buffer as well as the main memory, and the high-speed buffer is allowed to perform a data access with the DMA device or an external bus master. Therefore, the DMA device/external bus master are separated from the host data bus.

REFERENCES:
patent: 5289584 (1994-02-01), Thome et al.
patent: 5293603 (1994-03-01), MacWilliams et al.
patent: 5448558 (1995-09-01), Gildea et al.
patent: 5519839 (1996-05-01), Culley et al.

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