Bus control device comprising a plurality of isolatable segments

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3642405, 3642407, 307112, G06F 1340

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active

049224093

ABSTRACT:
A bus control device for a central processing unit (CPU) comprising a plurality of isolatable segments, which permits the transfer of data from one segment to another two adjacent segments being connected with one another via switches (S01, S11, S02, S12) controlled by a selection signal (C12, C23), an amplification device (A1, A2, A3) controlled by an actuation signal (CA1, CA2, CA3) being associated with each bus segment for amplifying the voltages that appear on the lines (B01, B11, B02, B12, B03, B13) of this segment, said control device being characterized in that it includes slaving means (12, 13, 16, 22, 23, 26) for actuating the amplifier of any one segment is response to the actuation of the amplifier of a segment adjacent to the this segment and in reponse to the selection signal (C12, C23) for the switches that connect this segment to said adjacent segment.

REFERENCES:
patent: 4296469 (1981-10-01), Gunter et al.
patent: 4302642 (1981-11-01), Hruda et al.
patent: 4583088 (1986-04-01), Bux et al.
patent: 4635192 (1987-01-01), Ceccon et al.
patent: 4737656 (1988-04-01), Grottlieb
patent: 4745300 (1988-05-01), Kammerer et al.
Patent Abstracts of Japan, vol. 7, No. 35 (p. 175) [1180], (listing Japanese Patent 57-187726, Matsushita Denki Sangkok.K, Nov. 18, 1982).

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