Bus control device

Details Bus control device Bus control device

1998-02-19

2001-07-31

Marcelo, Melvin (Department: 2663)

Multiplex communications

Pathfinding or routing

Store and forward

C710S027000

Reexamination Certificate

active

06269102

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus interface device.
2. Description of the Background Art
FIG. 11
is a block diagram showing a data processing system of an NIC (Network Interface Card) according to a background art. As the NIC, there is shown, for example, an ATMLAN board
1
(hereinafter referred to as a “board
1
”).
In the processing system, data transfer from a host memory
22
to a local memory
3
provided on the board
1
is performed through the following procedure.
Firstly, a host CPU
21
sends a source address SA, a destination address DA, and a data length DL of data to be transferred from the host memory
22
, to a configuration register
15
provided on a bus interface LSI
1
a
in the board
1
through a buffer
2
a
provided on a host bus bridge
2
. For convenience, these data transfers are shown by the arrows in the figure, but in practice, they are performed through a host bus
100
.
From a host bus DMA controller
12
on the bus interface LSI
1
a
in the board
1
, a request BQH to acquire the host bus
100
is transferred to a host bus arbiter
2
b
on the host bus bridge
2
. The host bus arbiter
2
b
examines whether the host bus
100
may be acquired by the host bus DMA controller
12
. If practicable, the host bus arbiter
2
b
sends a use permission GNTH of the host bus
100
to the host bus DMA controller
12
. In practice, the request BQH and the use permission GNTH are also sent through the host bus
100
.
The host bus DMA controller
12
which has acquired the host bus
100
sends the host memory
22
an output request RQ and the source address SA obtained from the configuration register
15
(actually through the host bus
100
). Data stored in the source address SA is sent to a data transfer buffer
11
a
on the bus interface LSI
1
a
through the host bus
100
.
When the data transfer buffer
11
a
is full, full signals FULL are sent to a local bus DMA controller
13
on the bus interface LSI
1
a.
The local bus DMA controller
13
sends a local bus arbiter
4
on the board
1
a request BQL to acquire a local bus
101
. The local bus arbiter
4
examines whether the local bus
101
may be acquired by the local bus DMA controller
13
. For example, it checks if the local bus
101
is already acquired by a protocol processor
5
. If practicable, the local bus arbiter
4
sends a use permission GNIL of the local bus
101
to the local bus DMA controller
13
. The local bus arbiter
4
may be provided on the bus interface LSI
1
a.
The local bus DMA controller
13
which has acquired the local bus
101
sends the local memory
3
an input request WQ and the destination address DA obtained from the configuration register
15
. Data stored in the data transfer buffer
11
a
are sequentially transferred to the local memory
3
through the local bus
101
and then held in the destination address DA.
Thus when data transfer from a host memory to a local memory is performed through a host bus and a local bus, the data transfer buffer
11
a
always causes delay in the background art. In addition, the host bus DMA controller
12
and the local bus DMA controller
13
operate independently, so that latency in bus acquisition occurs in both of the host bus and the local bus. This hinders improvement of data transfer rate.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a bus control device intervening between first and second buses comprises: a first path and a second path whose data transfer latency is larger than that of the first path, one of which being selectively connected between the first and second buses; a first bus DMA controller for controlling the first bus; a second bus DMA controller for controlling the second bus; and a data transfer controller for controlling the first path to be connected between the first and second buses when the first bus DMA controller can acquire the first bus and the second bus DMA controller can acquire the second bus.
According to a second aspect of the present invention, in the bus control device of the first aspect, the first bus DMA controller sends a request to acquire the first bus to a first bus arbiter for arbitrating an entity that acquires the first bus, the second bus DMA controller sends a request to acquire the second bus to a second bus arbiter for arbitrating an entity that acquires the second bus, and the first and second bus arbiters send permissions to acquire the first and second buses, respectively, to the data transfer controller.
According to a third aspect of the present invention, the bus control device of the first aspect further comprises a configuration register for storing a data length of data to be transferred between the first and second buses.
According to a fourth aspect of the present invention, the bus control device of the first aspect further comprises a configuration register for storing a destination address of data to be transferred between the first and second buses.
According to a fifth aspect of the present invention, the bus control device of the first aspect further comprises a configuration register for storing information indicating a type of data to be transferred between the first and second buses.
According to a sixth aspect of the present invention, in the bus control device of the first aspect, the first path has no buffer and the second path has a buffer.
According to a seventh aspect of the present invention, in the bus control device of the sixth aspect, the data transfer controller receives a data length of data to be transferred between the first and second buses and, when the data length is larger than a given length, the second path is connected between the first and second buses even if the first and second bus DMA controllers can acquire the first and second buses, respectively.
According to an eighth aspect of the present invention, in the bus control device of the seventh aspect, the data transfer controller includes: a comparator for outputting a comparison signal that is activated when the data length is not larger than the given length; and logical circuits for ANDing the comparison signal, a first use permission signal indicating that the first bus DMA controller can acquire the first bus, and a second use permission signal indicating that the second bus DMA controller can acquire the second bus, thereby sending a control signal to the first and second bus DMA controllers.
According to a ninth aspect of the present invention, in the bus control device of the sixth aspect, the data transfer controller receives a destination address of data to be transferred between the first and second buses and, when the destination address is outside of a prescribed range, the second path is connected between the first and second buses even if the first and second bus DMA controllers can acquire the first and second buses, respectively.
According to a tenth aspect of the present invention, in the bus control device of the ninth aspect, the data transfer controller includes: a comparator for outputting a comparison signal that is activated when the destination address is in the prescribed range; and logical circuits for ANDing the comparison signal, a first use permission signal indicating that the first bus DMA controller can acquire the first bus, and a second use permission signal indicating that the second bus DMA controller can acquire the second bus, thereby sending a control signal to the first and second bus DMA controllers.
According to an eleventh aspect of the present invention, in the bus control device of the sixth aspect, the data transfer controller receives a type of data to be transferred between the first and second buses and, when the type is not a specified one, the second path is connected between the first and second buses even if the first and second bus DMA controllers can acquire the first and second buses, respectively.
According to a twelfth aspect of the present invention, in the bus control device of the sixth aspect, the data transfer controlle

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